Note: this course's goals and objectives are based on the Association for Computing Machinery (ACM)'s Computing Curricula 2013, mostly in the knowledge area of Architecture and Organization.
Learning objectives with a
strikethrough have been omitted in Fall 2017 due to the fires.
Exam 1: Introduction; Metrics; Assembly language
Introduction (Sec. 1.1–1.5)
- Identify the major domains of computing (embedded, desktop, server, etc.).
- Based on the requirements of each of these domains, analyze the appropriateness of different hardware and technologies for each domain.
- Define and explain vocabulary related to program translation and execution, such as compiler, assembler, assembly language, and machine language.
- Define vocabulary related to data storage, such as bit, byte, KB, MB, GB, and TB.
- Explain (at a high level) the interactions among I/O devices, the processor, and memory.
- Classify specific devices as I/O, processor, or memory.
Metrics (Sec. 1.6–1.10)
Metrics: Processor-specific metrics
- Apply the classic (single-core) processor performance formula.
- Apply the classic processor power and energy consumption formulas.
- Explain the implications of the "power wall" in terms of further processor performance improvements and the drive towards harnessing parallelism.
- Evaluate performance in terms of latency and throughput/bandwidth, and determine which metrics are appropriate for different uses.
- Express relative performance in terms of speedup.
- Explain the circumstances in which a given system performance metric is useful.
- Explain the inadequacies of benchmarks as a measure of system performance.
- Assess systems' performance, power, and cost in a given situation.
- Critically examine claims about systems' performance, power, and cost.
Assembly (Ch. 2.1–2.9, 2.12–2.14)
- Summarize how instructions are represented at both the machine level and in the context of a symbolic assembler.
- Show how fundamental high-level programming constructs are implemented at the machine-language level.
- Explain different instruction formats, such as addresses per instruction and variable-length vs. fixed-length formats.
- Explain how subroutine calls are handled at the assembly level.
- Write simple assembly language program snippets using...
- arithmetic operations
- logical operations
- memory operations
- conditional operations
- functions and the call stack
- string processing and manipulation
Exam 2: Processor implementation (basic and pipelined); AMAT and locality
Basic Processor Implementation (Ch. 4.1–4.4)
- Explain the organization of the classical von Neumann machine and its major functional units.
- Describe how an instruction is executed in a classical von Neumann machine.
- Trace the execution of instructions and programs on a simple processor implementation.
- Modify the simple processor implementation to accommodate additional instructions.
- Compare alternative implementations of datapaths.
Pipelined Processors (Ch. 4.5–4.9)
- Trace the execution of instructions and programs on pipelined processor implementations.
- Quantitatively compare the performance of programs on pipelined and non-pipelined processors.
- Explain basic instruction level parallelism using pipelining and the major hazards that may occur.
- Explain the concept of branch prediction and its utility.
- Quantitatively evaluate the performance of programs on systems that use mechanisms like forwarding and branch prediction to mitigate these hazards.
Exam 3: Memory hierarchy and virtual memory; I/O; parallelism
Caches (Ch. 5.1–5.4)
- Describe how the use of memory hierarchy is used to reduce the effective memory latency.
- Analyze the spatial and temporal locality of different programs.
- Compute Average Memory Access Time under a variety of cache and memory configurations and mixes of instruction and data references.
- Quantitatively and qualitatively reason about the effects of cache block size, mapping scheme, replacement policy, and write policy on the performance and complexity of the hardware.
- Trace the cache state, including the mapping of memory addresses to cache blocks, for a pattern of memory references.
Virtual Memory (Ch. 5.6–5.8) Explain the workings of a system with virtual memory management. Trace the state of the page table and TLB, including the mapping of virtual to physical addresses, for a pattern of memory references. Calculate the required size of the page table for a given set of design decisions. Trace the steps in handling a page fault. Explain how VM allows protection and isolation.
I/O and Reliability (Ch. 4.9, 5.2, 5.5, 5.11, online readings)
- Evaluate I/O throughput and latency.
Apply the classic MTTF equation.
- Describe data access from a magnetic disk drive.
Apply the classic equation for magnetic disk performance.
- Explain (at a high level) how flash memory works.
- Compare the pros and cons of different storage types, and evaluate which is better for a given purpose.
- Quantitatively compare the performance and fault-tolerance of different approaches to RAID for different I/O access patterns.
Parallel Hardware and Software (Ch. 4.10, 5.10, 6)
- Define speedup and efficiency, and explain the notion of an algorithm's scalability in this regard.
- Describe the relevance of scalability to performance.
- Apply Amdahl's Law and Gustafson's Law and analyze their limitations and implications.
Explain the need for cache coherence and trace a simple cache coherence protocol. Explain (at a high level) how GPUs work and what types of problems they are good at.